Static Random Access Memory (SRAM) cells are one of the most popular ways to store data in electronic systems. Accordingly, embedded SRAM cells are vital building blocks in integrated circuits. SRAM cells are popular to implement because they provide high operational speed, robust data storage, and ease of integration.
SRAM arrays often occupy a significantly large portion of a chip's die area, making an SRAM cell an important block in terms of area, yield, reliability and power consumption. With increasing demand for highly integrated System on Chip (SoC) design, improving various aspects of embedded SRAM cells has received a significant interest.
The most popular SRAM cell configuration is a six transistor (6T) SRAM cell, due largely to its high operational speed and robust data storage. Referring to FIG. 1a, the 6T SRAM cell is illustrated. The 6T SRAM cell comprises four transistors configured to provide a pair of complementary storage nodes and two dedicated access transistors, each configured to access a corresponding one of the storage nodes.
Accordingly, a four transistor (4T) SRAM cell has been developed. Referring to FIG. 1b, the 4T SRAM cell is illustrated. The 4T SRAM cell comprises two drive transistors configured to provide a pair of complementary storage nodes and two dedicated access transistors, each configured to access a corresponding one of the storage nodes. Although the 4T SRAM cell reduces the space required to implement the SRAM cell, using only two drive transistors results in poor stability. Specifically, in this configuration the stability of the SRAM cell depends on the relative leakage through dedicated access and driver transistors. Therefore, threshold voltage fluctuations of transistors can affect the stability of the cell significantly. In extreme situations, the SRAM cell may lose its data.
Although the 6T SRAM cell is the most common memory cell, other cells have been created with the goal of higher stability and robustness. For example, referring to FIG. 10, a prior art ten-transistor (10T) soft error robust (SER) SRAM cell is shown. When ionizing radiation consisting of energetic cosmic neutrons and alpha particles strike an SRAM cell they generate a large number of electron hole pairs. Depending on the location of the particle strike, the deposited charge may be collected by a node in the SRAM cell. If sufficient charge is collected the SRAM cell can switch its logical state, which is called a soft error. Accordingly, the illustrated circuit comprises eight transistors configured to provide two pairs of complementary storage nodes. The redundant storage nodes provide the 10T SRAM cell with a robustness to soft errors. In addition to the core eight transistors which create the robust storage cell, two dedicated access transistors are provided to couple two of the four nodes in the storage cell to a pair of bitlines (BL and BLB).
Yet further, referring to FIG. 16, a state-of-the-art dual-interlocking storage cell (DICE cell) DICE cell also provides robustness to soft errors. Data is stored on multiple nodes and the DICE cell is immune to single node upsets. However, the DICE cell requires twice as many transistors to implement as the standard 6T SRAM circuit, making it expensive in terms of both area and power.
Irrespective of the storage cell which holds the data it is desirable to implement an SRAM cell with a minimal number of transistors while maintaining stability at the storage nodes.